How to design an integrated PowerMos Driver?

[gilbertomaldito]

POWER MOS gate driver

How to design an integrated PowerMos Driver.... My powerMOS cgs is quite large...(IRF730). Please help me how to design this properly.

For my initial design, I used inverter buffers with increasing sizes from
(first inverter) m=1,
2nd inverter : m=3,
3rd m=9,
4th m=81,
m=246, and so on. My W/L is 8u/2.5u for PMOS and 4u/2.5u for NMOS.
But my gate signal still not perfect, the time when it must be fully 10v, half of the time it stays in 6V. ex. for ton=2us , gate voltage must be 10v for 2us, but before it reaches 10v, voltage stays at 6v for 1us or worse. This is so abnormal.

I dont know if this is something about the driver or about the Buck topology.
But I just feel it is about the buffer.

 

[skowe26]

POWER MOS gate driver

Hi,

Have you tried running simulation with only the gate driver and power mosfet?
What is your Boostrap voltage?

I think your gate length (2.5u) is long. Make it smaller. What technology process are you using?

Regards.

 

[checkmate]

Re: POWER MOS gate driver

That "step" is a combination of the miller plateau effect and the reverse recovery of the low-side diode.

 

[gilbertomaldito]

POWER MOS gate driver

check mate
oh my... i think you have the point there...
can you elaborate more? can you help me describe whats happening ? and suggestions how to improve this? at first I thought it is about the driver, but when I increased the m upto m=2000, I still have the same problem. please please please...

skowe26, : yes I tried to do that. Simulating the gate Driver and the POWER MOS. The waveform I got is perfect square wave. But when I attached my current-mode-BUCK-converter circuit which has 2 switches( 1 NMOS and 1 ultrafast DIODE), the gate signal became so ugly. I am using 2.5u process

Added after 19 minutes:

i just finished my simulations with different sizes of my inverter tapper buffers, and I realized one thing. It did not solved my problem.
Btw, checkmate your photo is funny.

 

[hamradiolocator]

Re: POWER MOS gate driver

Thanks for sharing this serial.

 

[checkmate]

Re: POWER MOS gate driver

Dump the ultrafast diode and replace it with a schottky.
If possible, replace the NMOS with a PMOS.
Otherwise, try integrating a smaller but parallel PMOS on the high side.
If reverse recovery current is an issue, you will have to sacrifice some slew on the highside.

 

[gilbertomaldito]

Re: POWER MOS gate driver

checkmate, here is my circuit **broken link removed** .
from 1st page, You can see D10, originally it is MURS140T3 which is an ULTRAFAST RECTIFIER 1.0 AMPERE, 400 VOLTS, but when I tried to find a schottky which has the same current and voltage parameters, it seems I couldnt find one.

can you tell me the reason why is it preferable to use schottky?

btw, when I tested this DEMO board from NS. The gate of power mos has perfect square waves. (switching freq varies from fnominal=250kHz to fmax=350kHz)

When I tried to imitate the circuit with my own LED driver design, I experience Gate voltage problems. Please see attached photos,
1. fs=250khz ; vdd=80-100
2. fs=350-400khz, vdd=120-150

I feel for the slower fswitch, the stepping time is just fine and stays just for a very short time, but foor the high freq and high vdd, its very undesirable already.