Feb 8, 2005 #1 P ppenday Member level 4 Joined Jan 17, 2005 Messages 70 Helped 6 Reputation 12 Reaction score 2 Trophy points 1,288 Activity points 419 high speed d flip-flop site:edaboard.com hi all, can anyone tell me how to design a positive edge triggered D-flipflop with zero or minimum hold time.
high speed d flip-flop site:edaboard.com hi all, can anyone tell me how to design a positive edge triggered D-flipflop with zero or minimum hold time.
Feb 8, 2005 #2 P pra Member level 5 Joined Jan 8, 2005 Messages 85 Helped 6 Reputation 12 Reaction score 2 Trophy points 1,288 Activity points 672 tspc d-flip flops refer digital integrated circuits by Rabey
Feb 9, 2005 #3 K konqueror Full Member level 1 Joined Nov 27, 2004 Messages 96 Helped 2 Reputation 4 Reaction score 2 Trophy points 1,288 Activity points 808 D Flip Flop what is ur speed requirement and power dissipation specification.if u need high speed u can use TSPC d flip flop.otherwise u can implement a simple d flip flop using nand gates,which u can find in any digital logic and design text book.
D Flip Flop what is ur speed requirement and power dissipation specification.if u need high speed u can use TSPC d flip flop.otherwise u can implement a simple d flip flop using nand gates,which u can find in any digital logic and design text book.
Feb 15, 2005 #4 M mady79 Member level 5 Joined Mar 30, 2004 Messages 91 Helped 7 Reputation 14 Reaction score 1 Trophy points 1,288 Activity points 922 Re: D Flip Flop use transmission gates with reset enable option