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How to design a positive edge triggered D-flipflop ?

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ppenday

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high speed d flip-flop site:edaboard.com

hi all,

can anyone tell me how to design a positive edge triggered D-flipflop with zero or minimum hold time.
 

tspc d-flip flops

refer
digital integrated circuits by Rabey
 

D Flip Flop

what is ur speed requirement and power dissipation specification.if u need high speed u can use TSPC d flip flop.otherwise u can implement a simple d flip flop using nand gates,which u can find in any digital logic and design text book.
 

Re: D Flip Flop

use transmission gates with reset enable option
 

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