I need a Opamp with DC gain>80dB and Unity Gain frequency >100MHz. At first I try to design it with the class-A two-stage structure. but it is difficult to satifiy both the DC gain and phase margin.
Who can give me some advice about how to design. such as, if class-A structure can meet the request, or which kind of structure is more suitable. and so on. Thanks in advance!
May be the folded-cascode can meet the requriement.
First , the GBW is the function of power and technology(line width).
From the vlaue of Gain and GBW , the dominant pole is placed larger than the 10Mhz.
you can use two stage folded-cascode to split the requriement of Gain and GBW.
The first stage supply large current to enhance the transconductance and increase output resistance that results in the GBW incresing and the dominant shifting to large frequency.
many OTA architectures are suitable for your design. You have not mentioned several things about your OTA:
- power supply voltage & target technology (Vt of transistor)
- required output swing
- power dissipation requirement
Thank you. In fact the supply voltage is 3.3V, TSMC0.25 Process. (Vtn 0.52V, Vtp 0.85V) and load capacitance 1pF.
At first I set compensation capacitance to 250fF, but it seemed the phase margin is not enough(52), on the other hand if I increase the compensation capacitance, there seems a very large transistors must be adopted. So, do you have any suggestion?
of course you can. there're plenty of designs avaible for this kind of spec. it's NOT that hard. also, op needs to address other info like what is the load, power consumption, what is the amplifier for etc
If your output swing is not too tough, then try a folded-cascode with cascode boosting techniques, this shoud be provide you > 85 dB gain and > 150MHz GBW without too much problems. Or you can try two-stage opamp with first stage cascode structure, but this will consume much more power.
Thank you. In fact the supply voltage is 3.3V, TSMC0.25 Process. (Vtn 0.52V, Vtp 0.85V) and load capacitance 1pF.
At first I set compensation capacitance to 250fF, but it seemed the phase margin is not enough(52), on the other hand if I increase the compensation capacitance, there seems a very large transistors must be adopted. So, do you have any suggestion?