How to design a DDR3 interface

Similar threads

• A

  Swapping DDR3 pins to FPGA

  • Started by aminpix
  • May 29, 2024
  • Replies: 8

  PLD, SPLD, GAL, CPLD, FPGA Design
• Y

  interfacing between Customized AXILITE master block to DDR3 using Microblaze

  • Started by yayasinjab
  • Jun 20, 2024
  • Replies: 1

  PLD, SPLD, GAL, CPLD, FPGA Design
• E

  Is there anything that converts verilog to resistor, capacitor level design?

  • Started by electronicslab
  • Sunday at 2:41 PM
  • Replies: 1

  PLD, SPLD, GAL, CPLD, FPGA Design
• G

  can we design FPGA?

  • Started by gary36
  • Tuesday at 5:36 AM
  • Replies: 16

  PLD, SPLD, GAL, CPLD, FPGA Design
• A

  [SOLVED] How to test FPGA before soldering it?

  • Started by aminpix
  • Jul 19, 2024
  • Replies: 12

  PLD, SPLD, GAL, CPLD, FPGA Design