Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

How to describe in DFT compilto use external reference clock to pll as a scan clock?

Status
Not open for further replies.

chis4yu

Newbie level 4
Newbie level 4
Joined
May 23, 2020
Messages
6
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
74
Hi,

I have a pll which can bypass the pllout with input reference clock.
So when I force bypass=1, then the input reference clock is output to the pllout.

How to describe for DFT compiler this special connection and treat the reference clock as a scan clock ?

set_dft_signal -view existing_dft TestMode -port Xscanmode_i -active 1
set_dft_signal -view existing_dft ScanClock -port Xclkref_r_i

so the Xclkref_r_i is bypassed to the pllout when Xscanmode_i=1
should the scanclock actually be defined at the output of the pll due to this special mode ?

UPDATED SCANCLOCK DEFINITION
set_dft_signal -view existing_dft ScanClock -hookup_pin {i_pll/pllout}

Thanks,

David
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top