How to delay a clock signal having a period T by T/4 ?

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Re: Delaying the Clock


For delay clauses .. as mentioned, by guideline, it's not recommended to be coded in RTL .. if you need an evidence, please refer to RMM ..

Delays as I said, should be inserted (if needed) at the backend .. not at the front-end .. In synthesizable RTL code, clock nets are normally considered ideal nets, with no delays.

For wire-load models, they are not practical for big designs .. it's been years since people replaced it with physical synthesis .. wire-load models are no more than mathematical solution to backend delays .. while physical synthesis is much closer to reality as it indeed maps the routes during the synthesis process ..

Formal verification can't replace functional verification .. Formal verification is used in cases in which you want to compare 2 different representations of your design without going through details .. for example, you have an RTL and its netlist .. the original RTL is already verified .. and now you want to verify the netlist .. you don't need to go again through the whole dynamic/functional simulation to verify the netlist .. all you need to do is to formally verify this netlist against the original RTL .. which is by turn already been verified ..
 

Re: Delaying the Clock

ok, so we need the advice of someone from backend still

but how about having different clocks, shouldn't this work fine?!

omara007 said:
B.T.W There is also a different approach .. which is to go for formal verification instead of functional verification .. this hugely saves time ..
Click to expand...

i just want to know where this fits in, that's all.. i know about formal verification and its different approaches, but i need some elaboration about this sentence
 
Re: Delaying the Clock


Different approach in simulating the netlist => no need to dynamically simulate it ..
Did I manage to make myself clear ?


What do you exactly want to ask regarding the 2 different clocks ? .. I couldn't get the question ..
 
Re: Delaying the Clock

aha...so the mentioning of the formal verification part was for the netlist...and that the dynamic verification can be formal instead (equivalence checking)

...about the different clocks, i was just saying that maybe this can be a solution..
to have different clocks in the design (one for the main blocks and one for the delay part...) by adding clock dividers for instance...!
 

Delaying the Clock

u can use dvided by m counter to dlay clock
in our project from spartan 3 kit 50mhz clock
we r getting 1hz clock using 25 bit counter
 

Re: Delaying the Clock


Thanks Salma and Amara for these valuable informations.
Unfortunately the solution proposed using counter is not possible. In fact I have a set of signal generated directly from a unique Clock signal. Suppose that CLK is the frequency of the clock.
I generated from this clock the following signals having the following frequencies:
CLKbar
CLK/2,
(CLK/2)bar,
CLKbar/2,
Note that the speedest clock is CLK and CLKbar.
The counter is normaly used for frequency division and this is not my goal.

In addition I forgot to precise that I'm working at transistor level and not with FPGA.
 

Re: Delaying the Clock


Clock divider has completely nothing to do with phase shifting a certain clock by a fixed delay .. unless you have a complete circuit that generates a slower clock .. and with some XORing you can generate a third clock with T/4 phase shift from the original one .. and I still don't believe it's achievable ..

The buffer insertion was an acceptable solution given it's not coded in the front-end .. I believe we made this point clear enough .. unless a backend guy has another extra input to this issue ..
 

Re: Delaying the Clock

omara007 said:
unless you have a complete circuit that generates a slower clock .. and with some XORing you can generate a third clock with T/4 phase shift from the original one ..
Click to expand...

yah, that's what i meant...a completely different circuit done for this!


omara007 said:
The buffer insertion was an acceptable solution given it's not coded in the front-end .. I believe we made this point clear enough .. unless a backend guy has another extra input to this issue ..
Click to expand...

mm..we're looping again...LOL
YES... we've settled already on buffer insertion...but if he has to do it all on his own, then he'll have to learn how to do place and route...and that's quite "tedious"...so i just thought it'd be better to find something to be done in front end

anyway....
omara007 said:
I believe we made this point clear enough
Click to expand...

berra7a 3aleina shwayya ya mohammad...e7na benet3alem lessa
wa7da wa7da
 
Re: Delaying the Clock

salma ali bakr said:
berra7a 3aleina shwayya ya mohammad...e7na benet3alem lessa
wa7da wa7da
Click to expand...

For that reason I'm looping
 
Re: Delaying the Clock

Ok, i understand that we agreed that the solution is to indtroduce the delay at physical level using buffers insertion with the appropriate transistor sizing.
Is that the only one solution ?
 

Re: Delaying the Clock


ya fandem rabena yekremak w inshaAllah neb2a more experienced like you soon w man7'alekshee te "loop" abadan...LOL
 

Delaying the Clock

FIR all pass filter
 

Re: Delaying the Clock

i didn't try it before, but the idea is to create a filter that have a flat amplitude response and a 90degree phase shift at the desired frequency, this can be analog or digital design as far as i know this is used in quadrature modulators, try searching for all pass filters


sorry, i was using a friends account "roni9"
 

Re: Delaying the Clock


Good idea, but digital phase shifters contribute to considerable amount of logic .. this logic is normal when applied to a data signal that needs to be phase-shifted .. Yet, if this solution is applied to a clock path, the clock tree will then need more effort for balancing and synchronization.

Moreover, clock tree is the most dynamic circuit on the chip, and is considered the most power consuming circuit. If you want to insert extra logic along this tree, be prepared for the huge power that will be consumed in switching activities.

Another thing deserves to be mentioned .. delay buffers are composed of inverters .. while more complicated phase shifters may even contain multipliers .. with a single multiplier composed of several hundreds of logic gates ..

In some special cases, the modulator/filter can be implemented using LUT's instead of multipliers.


safwatonline: if you have a simple digital phase shifter circuit, please do post it here.
 

Delaying the Clock

yep, of course it will be more area and power than a buffer, so i think it depends on how accurate u need this shift.
Sorry, but i don't have simple phase shifter circuit, but i think i heard something talking about "hilbert transform" for the implementation (i am not sure),but may be u r familiar with this name
 

Delaying the Clock

The solution using filter seems to be complicated in terms of implementation.
I wanna know more about the performance of this solution. By performance i mean delay introduced by the FIR and stability of the signal.
Could you safwat give us more details about the FIR ?
 

Delaying the Clock

Now I am learning to study aldec AHDL, I would like to know use the spartan DCM. anybody does it know how to use and function simulation?
 

Re: Delaying the Clock

it let me remember the DDR/DDR2/DDR3 's DLL, 1/4 T delay for PVT .
 

Re: Delaying the Clock

master_picengineer said:
Ok, i understand that we agreed that the solution is to indtroduce the delay at physical level using buffers insertion with the appropriate transistor sizing.
Is that the only one solution ?
Click to expand...

I don't think inserting buffer is a solution. You can size it to give it exactly T/4 delay, but only at one corner of PVT. But in actual silicon, PVT is going to change. So you won't have exact T/4 delay in a lot of parts of same design.

The right way is to use DLL - Delay locked loop. It can give you shifts in exact phase of input clock, as you may need, like 1/2, 1/4, 1/8th phase shift.
 

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