How to delay a clock signal having a period T by T/4 ?

[master_picengineer]

Delaying the Clock

Hi member,
I have to delay a clock signal having a period T by T/4. Could someone tell me how ?

 

[shnain]

Re: Delaying the Clock

use a buffer !

 

[kavitha_bonthu]

Re: Delaying the Clock

you can try by phase shifting the clock

 

[master_picengineer]

Delaying the Clock

Thanks for you Shnain and kavitha_bonthu,
Could you please elaborate your replies ?

 

[Old Nick]

Re: Delaying the Clock

I don't think there is an easy way to do this,

You're going to have to multiply the clock using a PLL, so you get an edge in the right place 0+t/4.

Then you'll have to create some logic to make your delayed clock from this.

 

[melc]

Re: Delaying the Clock

Roboclock:
https://www.physics.ohio-state.edu/~hughes/cdf_osu/xft/documents/robo.pdf

take a deep look, there are hundreds of IC https://www.cypress.com/portal/serv...09&PageID=215&gid=1&fid=27&category=Roboclock

 

[salma ali bakr]

Re: Delaying the Clock

what i know is that you can insert a buffer to do that
but i haven't done it before ...so i can't give you any definite "tried" answers
but it isn't that easy...so it's better to divide your clock by 4 then maybe use a flipflop

 

[mouzid]

Delaying the Clock

Hi,

I think that buffer insertion is the only one solution.

 

[master_picengineer]

Delaying the Clock

Hi,
Special thanks for all of you.
The concerned clock is the speedest one among all the clocks used and it is not possible to adopt the solution proposed by old Nick and which consist in multiplying the clock frequency, inverting the resulting signal then dividing it by 2.
This will require the use of a PLL for frequency multiplication.

Could someone clarify the mean of buffer ? do you mean a set of inverter ?

 

[shelby]

Delaying the Clock

Yes a buffer is a set of invertere. But using a buffer means your 1/4 cycle delay will scale differently across various PVTs. You may end up with something like this:

BCS 1/8 cycle delay
TYP 1/4 cycle delay
WCS 3/8 cycle delay

 

[omara007]

Delaying the Clock

Buffer insertion is not done in the RTL .. this is usually done in the backend .. If you want to simulate your design with the delayed clock at the front-end level, just add a normal non-synthesizable delay in your testbench .. then, when it comes to real implementation, pass the delay information to the backend guys to add the buffer to this clock branch ..
Buffer insertion is well-known for the backend people .. they usually use it as an efficient technique to balance their clock trees ..

 

[Zerox100]

Re: Delaying the Clock

if you have DCN on your FPGA it's so easy. Feed the clock to DCM. set DCM shift phase as you wanted and use output clock and a register for shifting.
It's so easy

 

[omara007]

Re: Delaying the Clock

if you have DCN on your FPGA it's so easy. Feed the clock to DCM. set DCM shift phase as you wanted and use output clock and a register for shifting.
It's so easy

This is just in case that he's desinging for FPGA .. but for ASIC, it's a different story ..

 

[mouzid]

Re: Delaying the Clock

if you have DCN on your FPGA it's so easy. Feed the clock to DCM. set DCM shift phase as you wanted and use output clock and a register for shifting.
It's so easy

This is just in case that he's desinging for FPGA .. but for ASIC, it's a different story ..

yes, in fact.

 

[shnain]

Re: Delaying the Clock

Buffer insertion is not done in the RTL .. this is usually done in the backend .. If you want to simulate your design with the delayed clock at the front-end level, just add a normal non-synthesizable delay in your testbench .. then, when it comes to real implementation, pass the delay information to the backend guys to add the buffer to this clock branch ..
Buffer insertion is well-known for the backend people .. they usually use it as an efficient technique to balance their clock trees ..

How about post-synthesis STA, how will they know about this delay ?

 

[omara007]

Re: Delaying the Clock

Buffer insertion is not done in the RTL .. this is usually done in the backend .. If you want to simulate your design with the delayed clock at the front-end level, just add a normal non-synthesizable delay in your testbench .. then, when it comes to real implementation, pass the delay information to the backend guys to add the buffer to this clock branch ..
Buffer insertion is well-known for the backend people .. they usually use it as an efficient technique to balance their clock trees ..

How about post-synthesis STA, how will they know about this delay ?

I believe there is no problem in post-synthesis STA .. it will be the same as pre-synthesis STA .. the only thing is that you are going to use the netlist instead of the rtl .. in both cases, you still don't have the buffers inserted yet ..

Any backend guy has a comment on that ?

 

[shnain]

Re: Delaying the Clock

I believe there is no problem in post-synthesis STA .. it will be the same as pre-synthesis STA .. the only thing is that you are going to use the netlist instead of the rtl .. in both cases, you still don't have the buffers inserted yet ..

There is no pre-synthesis STA !

 

[salma ali bakr]

Re: Delaying the Clock

well
you can just use delay clauses in your HDL
then in the synthesis, give constraints about this delay
the tool will generate buffers needed to fulfill it
so the post-synthesis simulation would take into account the delay
then in the place and routing, the tool would just throw all the buffers inserted
but will take the same constraints you gave to the synthesis tool
and it'll insert the buffers on its own as needed

 

[omara007]

Re: Delaying the Clock

well
you can just use delay clauses in your HDL
then in the synthesis, give constraints about this delay
the tool will generate buffers needed to fulfill it
so the post-synthesis simulation would take into account the delay
then in the place and routing, the tool would just throw all the buffers inserted
but will take the same constraints you gave to the synthesis tool
and it'll insert the buffers on its own as needed

As an RTL guideline :

Avoid hand instantiating clock buffers in RTL code. Clock buffers are normally inserted after synthesis as part of the physical design. In synthesizable RTL code, clock nets are normally considered ideal nets, with no delays. During place and route, the clock tree insertion tool inserts the appropriate structure for creating as close to an ideal, balanced clock distribution network as possible.

I believe you were asking about STA not simulation, right ?

Anyhow, for post-synthesis simulation, it's no different from the pre-synthesis simulation .. still the netlist is going to replace the original RTL DUT with no problem .. in other words, still all the clocks are going to be generated inside the testbench which instantiates the netlist as a DUT (instead of the RTL in pre-synthesis) .. for that you can still delay the clock you want from inside the testbench and carryout a normal simulation ..

Yet .. I see no reason these days for post-synthesis simulation .. the synthesized netlist contains only component delays .. which contribute to nothing indeed in the final delay .. most of the people these days wait till they finish the P&R to go back for simulation .. in this case, the delay is going to be close to real .. otherwise, you will be wasting your time ..

Even, if you are going to use a wire-load model in synthesis .. this won't give you the accurate (or close to accurate) delays .. except in small designs ..


B.T.W There is also a different approach .. which is to go for formal verification instead of functional verification .. this hugely saves time ..

 

[salma ali bakr]

Re: Delaying the Clock

yah yah...i meant STA
sorry!

so one should avoid writing delay clauses....and not use wire-load models since they're inaccurate (except for small designs)...
so how should this be done then..???!!!

about formal verification: do you mean it would be better to replace all functional verification (simulations, STA, etc..)...by formal ways (equivalence checking, model checking, property monitors...etc) ?!