How to define the rise&fall time of clock in simulation?

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eggzhang

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Question just as the subject.

There is a saying regarding this question: The setting of the rise and fall time of clock is arbitrary, as long as your circuit can work with that setting. And the sharper the rising of the clock, will consume more power and add more harmonics to your circuit.

What do you thing of this saying?
 

"And the sharper the rising of the clock, will consume more power"

It's true since more current is used to charge or discharge the capacitor in sharper edge of clock.

But I don't understand why you are talking about harmonics here? Do you mean glitch noise on power supply? If the clock is used in some analog circuits such as switched-capacitor, the sharper clock is helpful for reducing harmonics.
 

Re: How to define the rise&fall time of clock in simulat

When you have sharper rise,fall times, the clock transition can easily couple to other sensitive nodes reducing SFDR in data converters. I guess this is what eggzhang refers to as harmonics of the clock.
 

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