how to define the loop bandwidth of Switching Regulators

[minaflying]

This question have puzzled me for long times.
for Switching Regulators (DC-DC converters) ,some times we only know the error amplyfier's bandwidth,because it's linear,that's easy to simulate and test.But for other models from PWM to output driver,they are working in switched mode not linear mode,how can we define or simulate their bandwidth? And then how to simulate the full closed loop bandwidth and loop gain?
thanks alot!

 

[Btrend]

Re: how to define the loop bandwidth of Switching Regulator

the average switching model can do the loop simulation, try search it in google.

 

[chip]

Re: how to define the loop bandwidth of Switching Regulator

you can refer to papers of middlebrook and ridley

or read the book- <fundamentals of power electronics>

 

[minaflying]

thanks,but how can I get this book

 

[minaflying]

Re: how to define the loop bandwidth of Switching Regulator

to Btrend: thanks for you ,can you tell me some detail about average swiching model.

 

[Btrend]

Re: how to define the loop bandwidth of Switching Regulator

there is a good book for ur question
https://www.amazon.com/exec/obidos/...pd_sxp_f/102-3625344-5195336?v=glance&s=books

 

[funster]

Re: how to define the loop bandwidth of Switching Regulator

generally, we select SMPS(switch mode power supply)'s bandwidth

equal to 1/6 switching frequency. because a SMPS's bandwidth

can't great 1/2 switching frequency in accordance with sampling theory.

for step down converter, if the current in the inductor is continuous,

then the circuit model is linear, you can analyze this circuit

by using linear circuit theory.


best regards

This question have puzzled me for long times.
for Switching Regulators (DC-DC converters) ,some times we only know the error amplyfier's bandwidth,because it's linear,that's easy to simulate and test.But for other models from PWM to output driver,they are working in switched mode not linear mode,how can we define or simulate their bandwidth? And then how to simulate the full closed loop bandwidth and loop gain?
thanks alot!

 

[VVV]

Re: how to define the loop bandwidth of Switching Regulator

First of all, the switching frequency is much higher than the bandwidth of the error amplifier and it is filtered out by the filter of the DC/DC converter. Thus, you only have a DC input (error amp output) and a DC output (the power supply output).

To get the transfer function, you start from the relation between the control voltage (error amp output) and duty-cycle. Then you link the duty-cycle to the output voltage. Add the effect of the inductor + output cap; they form a low-pass filter. Finally, consider the so-called ESR zero, which is due to the output cap's ESR.

To take a crude example, consider a buck regulator operating in continuous current mode, at a certain input voltage. Assume the control architecture is voltage mode, with the PWM using a ramp voltage of amplitude Vramp. Assume the duty-cycle can be varied linearly from 0 to 100% when the error amp's output, Vea sweeps the entire amplitude of the ramp, Vramp.

DC= Vea/Vramp

Because the switching frequency is much higher than the bandwidth, the switching action is "transparent". You simply see a change in the DC output voltage as a result of a change in the Vea output, another DC voltage.

Vout = Vin*DC=Vin*Vea/Vramp

The low frequency gain is
Vout/Vea=Vin/Vramp

The inductor with the output cap forms an LC tank, that is you will have two complex-conjugate poles due to the combination.
fccp=1/(2*π*√LC)

The output cap with its ESR will give you a zero at
fESR=1/(2*π*ESR*C)

As you can see, the transfer function will depend on the input voltage. You will have to calculate it for both the maximum and the minimum input voltage.

The Bode diagram of the transfer function would look like the one below.
For other architectures, the transfer functions will be different. For current mode, they are also calculated differently.

This only applies to the PWM, power stage and filter. The loop will include the error amplifier, whose characteristic will be designed starting from this transfer function. The goal is a stable design with adequate bandwidth and gain/ phase margins.

 

[babbage]

to vvv, how to get the loop gain according to the customer requirement? for example load reglation..
Thanks a lot!