How to define global variable in verilog?

[saurabhs]

Hi all
I wanna define global variable in verilog so that i can use them in different module.
How it can be done.
Thanks in advance.

 

[skyfaye]

Re: Global Variable in Verilog

With verilog, pretty much everything's "global". You can use hierarchical reference to access any variable in any module.

For example:

module glb_var_mod; // define all global vars in this module
reg glb_x = 1'b1;
endmodule

module dut;
glb_var_mod.glb_x = 1'b0; // change value of a global var
endmodule

- Hung

 

[Jack// ani]

Re: Global Variable in Verilog

With verilog, pretty much everything's "global". You can use hierarchical reference to access any variable in any module.

For example:

module glb_var_mod; // define all global vars in this module
reg glb_x = 1'b1;
endmodule

module dut;
glb_var_mod.glb_x = 1'b0; // change value of a global var
endmodule

- Hung

Very insightful indeed. Thanks!!

Curious to know can we do the same in VHDL too?

 

[ghazalaz]

Re: Global Variable in Verilog

With verilog, pretty much everything's "global". You can use hierarchical reference to access any variable in any module.

For example:

module glb_var_mod; // define all global vars in this module
reg glb_x = 1'b1;
endmodule

module dut;
glb_var_mod.glb_x = 1'b0; // change value of a global var
endmodule

- Hung

i did so but this error was the result:
Error on line 7 ) : near "=": syntax error, unexpected '=', expecting IDENTIFIER or TYPE_IDENTIFIER
what is this?

i did something like this another time on another project , and there was an error "Undersolved reference to 'glb_var_mod"
and what is this?!

 

[Laleh92]

Re: Global Variable in Verilog

Hi
Maybe you got this error because you didn't use 'always' or 'initial' blocks. Assigning values to reg must be in one of these blocks depending on situation.
For example:
module glb_var_mod; // define all global vars in this module
initial
reg glb_x = 1'b1;
endmodule

 

[dave_59]

Re: Global Variable in Verilog

Just a note that global variables are not synthesizable, and in general, not a good programming practice in any language.
If instead you really need a global value, use a `define in Verilog or a parameter declared in a package in SystemVerilog.