How to dectect the lock of PLL?

[leonwang]

I have a PLL and want to add the Lock_Detector block.
How to design the block?

If I use the D flip-flop, with the Fref to clk and Fout to D,
I could watch the output of it after a definited time.

But there is a question, because of the jitter, we have a
character named period jitter and that will make the
result fault.

So I wanna get some help about that.

Thank you all.

 

[electronrancher]

jitter will be defined mostly by the ripple voltage on the filter. use a small filter for very quick lock, your ripple and jitter will be larger.

look at it like this: for a VCO needing 1v/100MHz, you will have 1.0v on the filter node when CLK=OSC=100Mhz. A good idea is to set the filter large enough in order to keep the sawtooth ripple (from the charge pumps) smaller than 10mV, giving 1% ripple, and 1% jitter. no need to worry about random jitter until you make this case <0.1%, in which case your lock is very slow.

now since you know your jitter is 1%, you can use a pre-set cutoff time for checking the output of DFF. Set this to 2.5-3% of the clock time, and the output of your nand will be the lock signal you want.

YES - you have 1.5% of indeterminate state. this is called hysteresis, it is probably a good idea - cutting it closer like 0.5% you run the risk of giving many small false lock signals before finally settling to a steady-lock.