How to decrease the Ron (On resistance) with given NMOS parameters

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henry kissinger

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Given the NMOS model below from the Keysight ADS.
How do I decrease the Ron (On resistance) with given NMOS parameters, of course without changing the geometry of the NMOSFET (width and length)

 

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henry kissinger said:
Given the NMOS model below from the Keysight ADS.
How do I decrease the Ron (On resistance) with given NMOS parameters, of course without changing the geometry of the NMOSFET (width and length)
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Hello Henry,

By "given NMOS parameters, of course without changing the geometry of the NMOSFET", I guess you also mean without changing model parameters such as KP or VTO? Can you increase VGS to have a larger overdrive?
 

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For a given semiconductor process, basically the on-resistance is determined by the geometry so, if you can't change that, then I see no way to reduce the on-resistance.
 
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Channel ratio and device biasing are the only variables you can change if you expect a realistic circuit simulation result.
 

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- Lower the temperature
- Increase Vgs
- Use forward body bias
- Apply mechanical stress

The main / easiest parameter to decrease Rdson is the gate width, this is what power FET and PMIC IC designers use to make very low Rdson devices.
So saying "of course without changing the geometry" does not sound reasonable.
 

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Problem #1 is that all but one model param are left to default. You don't even know what they default to unless you read the ADS software docs, to know what should change.

At any rate this is not anybody's real device, just made-up sh*t, so feel free to add whatever additional fertilizer you like. If this is a "reality-facing" project then go chase some real device models.

W, L and m are always there for you.
 

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