How to debug "unbound" warnings in NCELAB ?

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chau0873

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Dear all,

I have a design in VHDL format, in the architecture, I called a component. The design of component is in Verilog format and have architecture, like below :
entity my_design is
...

architecture arch of my_design is
component hello
...

module hello (...)
{
inst_1 inst_hello (...)
}

module inst_hello (...)
{
}
Click to expand...

I used same worklib for NCVHDL and NCVLOG command. The same option (-64) is used for both NCVHDL and NCVLOG.

My understand is : the architecture (hello) for the entity is missed/lacked/un-compiled, or some mistakes in port name/size ... Is there any reason else ? How can I debug this warning ? Is there any option of NCELAB to show EXACTLY where the mistakes happens ?

May anyone help me ? Thank you so much.

Best regards,
 
Last edited:

Dear all,

I have solved this problem. Nothing wrong here. Let me explain how I have done. I have compiled all Verilog files(NCVLOG), then compile all VHDL files (NCVHDL), then elaborate (NCELAB) -> Unbound warnings.

I just need to compile Verilog files again, then run NCELAB. The warnings are disapeared ! But I haven't found what's the problem here

My above is just to describe my project. Actually, the real project is big (1498 files in VHDL and 10 files in verilog). Is this the reason ? I have used the same way for old project with the number of modules are less (~800 VHDL files). The same tool version of NCSIM has been used for both projects (INCISIVE 12.0.0.s004)

If you have any opinion, please share to me.
 

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