How to debug synthesis error in Verilog

[victoria_jitesh]

please any one tell me any good sites or material based on how to debug synthesis error in verilog.
Also tell me what are most common synthesis error in verilog and how to avoid it.

Thanks in advance

 

[echo47]

That's a really broad question! A huge range of problems can occur during synthesis, and the problems are all different depending on which synthesis tools you are using, and your personal experience level.

When you say "error" are you talking about error messages from the synthesis software? Or do you mean that the synthesis process runs smoothly, but the hardware doesn't behave as you expected?

The best resource for understanding synthesis problems is usually the manufacturer's web site. For example, Xilinx has an extensive Answer Database that has helped me solve many of the puzzling problems that I've encountered using Xilinx FPGAs.

 

[karikalan_t79]

only post map timing simulation will give you the idea