How to debug spurs on a delta-sigma synthesizers IC?

[TomSpade]

Delta-Sigma Synthesizers

Does anybody have a good paper on practical ways to debug spurs on a delta-sigma synthesizer IC? (Yes, we have them...and yes, I'm extremely worried.)

We have the basic problem...spur close to harmonics of the reference and limited access to the circuitry (with it being and integrated circuit and all).

...Thanks for the help

 

[Japp]

Re: Delta-Sigma Synthesizers

This is probably not of any help (so maybe i shouldn't post it..) But If you look in a book like Norsworthy´s "Delta-Sigma Data Converters". You will see that even higher order SD-modulators are tonal near the integer (ref harmonics) and all commercial SDMs on the market are also tonal (and much more tonal than they claim in their datasheets).
Then there are at least 8 Phd theses at the Internet. Some of these takes a large effort in reducing the spurs. (many different dither functions, phase detector architectures etc) but in the final measurements they all have large spurs.
De Muer and Steayart also published a book last year (CMOS Fractional-N Synthesizers) where they also ends with a lot of spurs and their solution is quote: "In practice, fractional division by numbers close to integer moduli must be avoided or the phase->current conversion must be highly linear" !!.
So one way is to do some frequency planning and choose a reference frequency high enough so your Integer does not fall into your frequency band. Or alternatively move the reference frequency close to Integers.

A realistic spur chart was once given by Dean Bannerjee from National (but removed again?) From the presentation "Advantages and pitfalls of using Fractional N PLLs" and shown below. As far as I remember the loop bw is 10 kHz. The darkblue (LMX247x) is a 4th order sigma delta modulator. The 'channel spacing' is the offset from an Integer frequency.
Finally I would say, if you do find a good solution please let me know