How to debug Assura LVS and can I run LVS after RCX?

[pfng]

Hi,
I have some questions regarding Assura LVS/RCX.

1) How to debug Assura LVS? To debug DIVA extraction, I used to use saveDerived and view the layer in the extracted view. But Assura there is no extracted view, so how to go about debugging?

2) Can I run LVS after RCX? This is to check if the extracted netlist with parasitics is well form. I had experience that the parasitic resistor is shorted to ground, drawing a lot of current.

3) My Assura LVS recognise resistors with the 2 terminals connected to the same terminal as malform devices. Why? How to by pass this?

Please advice.

 

[tsinghua]

Assura LVS/RCX

Assura provides its own debug tool. Just find the discrepancy and click the open tool button.
LVS should be chekced before RCX run.
The recognition of device is based on the rules file. You should check the rules file and give your question to the foundry support.