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you can use fifo and ram to be the interface of the data transferred in different clock domains.also ,handshaking is another way to solve the problem.attention: you must pay more attention to the judgement of write and read enable,comparison between write and read pointer must be made in differnt alock domains.
Hi,
sometime back I uploaded a paper "Fourteen ways to fool your synchronizer". It deals with various technqiues that deal with the asynchronous signals crossing clock-domains.You will find it even in GOOGLE. check it out...
Hi,
There are various ways by which you can avoid any kind of disasterous results in your hardware due to multiple clock domain. Few way to address such design are
1) We can have a buffer or fifo inbetween these 2 clock domains. So incase if on one clock read happens the there clock write can take place. But the depth of the fifo is an issue and need to be carefully planned.
(You can use an elastic fifo for that matter)
2) The next method can be use of handshaking. Like in one clock domain you ask for write request, the other clock domain gives inreturn grant then write occurs...similarly read can also take place.
3) The next method makes use of Gray code logic.
Synchronizaiton is for control signal and data path signals
for controlsignla u can use the methods like double synchronizer etc
while for data synchronozation use fifos
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