How to deal with process variation on bandgap vref

bandgap reference voltage process variation

Hi, everyone.
On purpose of cost down, the fab we choose is unstable.
After measuring the Vbe feature of its process on sample, a bandgap vref was designed. However, we found it's impossible to adjust to reach 0 TC vref at room temp.

The non-linear TC DC error and linear TC DC error had been considered.
But i am not sure all DC error was cancelled by adjusting.

Since it costs too much to measure the Vbe at various temp each lot, is it possible to reach the 0 TC vref at room temp using information at only the same temp?

If it is not clearly presented, pls let me know.
Thanks very much for any advice!

Best regards!
Lee

1v bandgap process variation

you can choose a more consistent fab, or you can laser trim the end product to achieve better tempco.

bandgap process

For all practical purposes, the tempco of the bandgap is second order. To fully define a second order function 3 points are required.

I will say that if your tolerances are at a point were the the second order effects can be ignored, then you can do it with a two temperature calibration. This may be able to be done with "self heating."

Fundamentally though, to calibrate out a second order tempco, will require 3 points.

ways to deal with process variation

You can trim in other ways than laser, the very high
accuracy bandgaps go as far as dense (EE)PROM cal
maps and I have done zener zap and fuse style trim
networks. You will need a minimum of two, one to get
tempco flat and one to correct for this step's change to
the output voltage value.

Your diffused resistors ar not mentioned as having
been characterized; these can have a very large
"contribution" of their own, are often not well
controlled in CMOS processes and the tempco will
vary with the sheets, potentially not well modeled
second order "effect" (if all you see is fixed TC1 and
TC2 values in the design kit, then no thought was
given to this).

The only time I tried to do a second order temp
compensation, it was a mess. The cubic term is not
something you want to count on foundry design kits
for at all. You may find it necessary to fit your own
models for all of the single-ended components (the
reference diodes, the resistors, possibly even the
startup circuit devices; think veriloga and many fun-
filled hours of curve-fitting) to do a really good job.

In my world I have to accept some degree of model
slop and design for a sub-bandgap reference that
comes off a divider, which I can make late-levels
selectable to center up the final design based on a
body of real data.

bandgap process variation

millwood, it's expensive indeed, thanks any way.

Thanks stefannm, i get yours.

Thanks dick_freebird for the detail reply.
However, it may be my future task to build my own models, right now, i have to work based on fab's.

It seems it is impossible to ... in only one temp point.

Packaging stress could cause random TC shifts. Also you may have some type of temperature sensitivity in the buffer stages following the bandgap.