[SOLVED] How to de-embed the influence of buffer in LNA testing

Why a Buffer is necessary ?? If you measure this LNA, Noise Figure Meter and Noise Source have already 50 Ohm Input/Output Impedances. NF should essentially be measured under Small Signal driven condition and therefore you don't need a extra buffer to drive it.
You have to prepare another set-up for IIP3. You cannot measure two quantities simultaneously.

BigBoss said:

Why a Buffer is necessary ?? If you measure this LNA, Noise Figure Meter and Noise Source have already 50 Ohm Input/Output Impedances. NF should essentially be measured under Small Signal driven condition and therefore you don't need a extra buffer to drive it.
You have to prepare another set-up for IIP3. You cannot measure two quantities simultaneously.

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Hello BigBoss
I agree with you about NF measurement. The NF does not depend on the load. However, the LNA needs to drive a 50Ω load when the IIP3 is measured. If there is no buffer, the voltage gain will be very low. I used an on-chip buffer to avoid the parasitic introduced by off-chip devices and board wires. The NF, gain, IIP3, and S11 should all be measured on one die. So I am looking for a set-up to solve them all.

Doesn't make sense to me. If your LNA has other output impedance than 50 ohm (unlikely, but possible), IIP3 measurement should be performed with nominal load impedance, e.g. using resistive matching circuit.

FvM said:

Doesn't make sense to me. If your LNA has other output impedance than 50 ohm (unlikely, but possible), IIP3 measurement should be performed with nominal load impedance, e.g. using resistive matching circuit.

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If an LNA is used in a receiver, the load of it would be a mixer. Consequently, it usually sees the gate of a transistor. So I think a buffer simulates well. Moreover, the buffer can drive the load.

No problem to use a buffer as load if you like. But you shouldn't complain about distortions created by the buffer.

My suggestion is however different.
1. Define the load impedance which you want to test IIP3 etc.
2. Design a respective passive test load

There is only one case when an LNA is mandatory to have a buffer, in case when the LNA is placed at long distance from the receiver input (e.g. when the LNA is placed near the antenna, and the antenna is placed on top of a building).
Otherwise, the LNA design can provide the desired output impedance without sacrificing other parameters.

FvM said:

No problem to use a buffer as load if you like. But you shouldn't complain about distortions created by the buffer.

My suggestion is however different.
1. Define the load impedance which you want to test IIP3 etc.
2. Design a respective passive test load

Click to expand...

I do not know what equipment I will use for testing IIP3. But usually, it will include a probe with 50Ω impedance. I think you mean output impedance matching. I am not sure whether this is suitable for integrated circuits. I think the matching network will consist of several off-chip components. Wires on PCB will cause other problems like parasitics and reflection. However, the working frequency is no more than 2GHz. Thank you, I will check it.

vfone said:

There is only one case when an LNA is mandatory to have a buffer, in case when the LNA is placed at long distance from the receiver input (e.g. when the LNA is placed near the antenna, and the antenna is placed on top of a building).
Otherwise, the LNA design can provide the desired output impedance without sacrificing other parameters.

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Thank you, but I think you are considering a different situation.
The LNA is in a receiver. And the whole receiver will be in one die, so no output impedance matching is designed. And here, I care about the voltage gain instead of S21. Now I want to measure the performance of the LNA, and the LNA cannot drive a 50Ω load (like a probe). So I put a buffer behind it.

To help us understand the possible test setup options, what is the nominal LNA load impedance?

FvM said:

To help us understand the possible test setup options, what is the nominal LNA load impedance?

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Supposing it drives the gate of an NMOS with an aspect ratio of 2/0.18*10. And the Vgs of it is 0.8V. The real part of its load is 456Ω, and the imaginary part of it is -4.37kΩ.
And now, I think I know how to do measurements. The idea is simple: I simulate the LNA with the designed buffer and idea buffer and record the difference. After measurement, I subtract the recorded difference from the measured results.

xiaowenrun said:

The LNA is in a receiver. And the whole receiver will be in one die, so no output impedance matching is designed. And here, I care about the voltage gain instead of S21.

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The old story, when analog IC designers believe that: when an RF receiver (or an RF transmitter) is built on a chip, internally is no need for RF power matching, and important is only the voltage gain (due to small distance between stages, they keep saying). Hard to understand that the mismatch loss (1−|Γ|^2) don't care a bit about voltage gain.
This tale is coming back, again and again, like a pandemic.