how to ctrl the operation of register

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anusha vasanta

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HI everyone,
i had a doubt help me, i had a tmp_reg of 128 bits in starting time that tmp_reg should contain a mic value of 128 bits , and from next onwards it should contain some other result, just like this it should run sequentially
eg:
tmp_reg= mic;
gen block
for(m=0;m<5;m=m+1)
assign b_0[m]=tmp_reg^d[(m*128)+127m*128)]
TOP(b_0[m],b_r[m])//instantiation
assign tmp_reg=b_r[m]

here everything i want is my block should run sequentially as per architecture point and my register for first m=0 it should contain tmp_reg with mic value and from next m=1 onwards tmp_reg should contain the instantiation result.
i was just troubling for implementing this.
just suggest me any help
thanku all
 

Before you write this code, I would suggest you to first pick up a good HDL book and read it.
The above piece of code is not sequential, and uses a combination of generate and for loops. U need to understand how HDL is interpreted as hardware, the syntax of several constructs (like generate & for loops) and when to use where.
 

I don't know about Verilog 2001. But I read verilog from Bhaskar. U can pick up any Verilog book I suppose maybe not focusing on V-2001.
 

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