TYPE SINTAB IS ARRAY(0 TO ROMSIZE-1) OF STD_LOGIC_VECTOR (NNCO-2 DOWNTO 0);
SIGNAL SINROM: SINTAB;
BEGIN
GENROM:
FOR idx in 0 TO ROMSIZE-1 GENERATE
CONSTANT x: REAL := SIN(real(idx)*MATH_PI/real(ROMSIZE));
CONSTANT xn: UNSIGNED (NNCO-2 DOWNTO 0) := CONV_UNSIGNED(INTEGER(x*real(ROMMAX)),NNCO-1);
BEGIN
SINROM(idx) <= STD_LOGIC_VECTOR(xn);
END GENERATE;
A function is possibly the more flexible way, and doesn't rely on rarely used VHDL constructs that are mostly ignored by text books.but do the setup inside a function, that way you can assign a constant instead of a signal
You can use whatever representation you want - usually people stick with floating or fixed point. You could use that equation to generate a look up table in VHDL quite easily, but you have to decide if you want fixed point or floating point for the output. The input (X) will have to be fixed point.
xi x sin(4pi x) sin_4pix_i
-128 -4.000 0 0
-127 -3.969 0.098 13
...
-112 -3.500 1.000 127 (saturated)
...
-1 -0.031 -0.098 -13
0 0.000 0.000 0
...
+127 3.969 -0.098 -13
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