How to create LEF file for ram_256x16A_typical_syn.lib for encounter

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JineshKB

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sir,
I have some libraries for memory like ram_256x16A_typical_syn.lib and but I don't have .LEF files for this modules can I generate LEF files for this libraries ?
 

You can only generate an incomplete LEF file as power connection information is missing in dot lib.
 

philewar said:
You can only generate an incomplete LEF file as power connection information is missing in dot lib.
Click to expand...

Sir,
I didn't understand what u said.I used this library in RTL compiler now I want to export it to cadence encounter and I don't have any LEF file which have information of this memory instance.

* CONFIDENTIAL AND PROPRIETARY SOFTWARE/DATA OF ARTISAN COMPONENTS, INC.
*
* Copyright (c) 2003 Artisan Components, Inc. All Rights Reserved.
*
* Use of this Software/Data is subject to the terms and conditions of
* the applicable license agreement between Artisan Components, Inc. and
* Taiwan Semiconductor Manufacturing Company Ltd.. In addition, this Software/Data
* is protected by copyright law and international treaties.
*
* The copyright notice(s) in this Software/Data does not indicate actual
* or intended publication of this Software/Data.
* name: SRAM-SP-HS SRAM Generator
* TSMC CL018G Process
* version: 2002Q2V0
* comment:
* configuration: -instname "ram_256x16A" -words 256 -bits 16 -frequency 250 -ring_width 2 -mux 16 -drive 12 -write_mask off -wp_size 8 -top_layer met6 -power_type rings -horiz met3 -vert met4 -cust_comment "" -left_bus_delim "[" -right_bus_delim "]" -pwr_gnd_rename "VDD:VDD,GND:VSS" -prefix "" -pin_space 0.0 -name_case upper -check_instname on -diodes on -inside_ring_type GND -libname "ram_256x16A"
*
* Synopsys model for Synchronous Single-Port Ram
*
* Library Name: ram_256x16A
* Instance Name: ram_256x16A
* Words: 256
* Word Width: 16
* Mux: 16
* Pipeline: No
* Process: fast
* Delays: min
*
* Creation Date: 2003-01-20 15:24:18Z
* Version: 2002Q2V0
*
* Verified With: Synopsys Design Compiler
*
* Modeling Assumptions: This library contains a black box description
* for a memory element. At the library level, a
* default_max_transition constraint is set to the maximum
* characterized input slew. Each output has a max_capacitance
* constraint set to the highest characterized output load. These two
* constraints force Design Compiler to synthesize circuits that
* operate within the characterization space. The user can tighten
* these constraints, if desired. When writing SDF from Design
* Compiler, use the version 2.1 option. This ensures the SDF will
* annotate to simulation models provided with this generator.
*
* Modeling Limitations:
* Due to limitations of the .lib format, some data reduction was
* necessary. When reducing data, minimum values were chosen for the
* fast case corner and maximum values were used for the typical and
* best case corners. It is recommended that critical timing and
* setup and hold times be checked at all corners.

this is the initial content of my library, I think this have some information on power connection.I don't know how to create an lef file pls help with this.
 

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