How to Create large Memory in VHDL

Code VHDL - [expand]
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type pbyte is array (0 to 511) of std_logic_vector (7 downto 0);  --pbyte is no of bytes in a page, each byte having 8 bits....
type mem_page is array (0 to 1023) of pbyte;                      -- total memory data type
signal page : mem_page :=(others=>(others =>(others => '0')));    -- TOTAL MEMORY !!

Code VHDL - [expand]
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----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    18:44:36 09/15/2012 
-- Design Name: 
-- Module Name:    memory - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity memory is
    Port ( rw,clk : in  STD_LOGIC;
           add : in  STD_LOGIC_VECTOR (9 downto 0);
           data : inout  STD_LOGIC_VECTOR (63 downto 0);
           busy1 : out  STD_LOGIC:='0');
--            aaa : inout integer );
end memory;
 
 
 
architecture Behavioral of memory is
type pbyte is array (0 to 511) of std_logic_vector (7 downto 0);  --pbyte is no of bytes in a page
type mem_page is array (0 to 1023) of pbyte;                      -- total memory type
signal page : mem_page :=(others=>(others =>(others => '0')));    -- TOTAL MEMORY !!
-- Temporary buffer
signal cu_add : std_logic_vector (9 downto 0);
signal cu_rw : std_logic;
signal count,add_int: integer :=0;
signal rep,busy : std_logic :='0';
begin
 
    add_int<= CONV_INTEGER(cu_add); --converting adderess to integer..
    busy1<=busy;
    
    assign : process(clk)
    begin
        if(rising_edge(clk))
        then
            if(busy='0')
            then
                cu_add<=add;
                cu_rw<=rw;
            end if;
        end if;
    end process assign;
            
    
    
    main : process(clk)
    begin
        if(rising_edge(clk))
        then
                        
            if(rep='1')
            then
                if(count<64)
                then
                    if(cu_rw='1')   -- Reading DATA
                    then
                        data <= page(add_int)(count) & page(add_int)(count+1) & page(add_int)(count+2) & page(add_int)(count+3) & page(add_int)(count+4) & page(add_int)(count+5) & page(add_int)(count+6) & page(add_int)(count+7);
--                  else      -- Writing DATA
--                      page(add_int)<=data;
                    end if;
                    count<=count+8;
                    if(count=64)
                    then
                        rep<='0';
                        count<=0;
                        busy<='0';
                    end if;
                end if;
            else
                busy <= '1';
                rep<='1';
                if(cu_rw='1')   -- Reading DATA
                then
                    data <= page(add_int)(0) & page(add_int)(1) & page(add_int)(2) & page(add_int)(3) & page(add_int)(4) & page(add_int)(5) & page(add_int)(6) & page(add_int)(7);
--              else      -- Writing DATA
--                  page(add_int)<=data;
                end if;
            end if;
            
        end if;
    end process;
        
 
end Behavioral;

Code VHDL - [expand]
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type ddr_model_t is protected
  impure function read( addr : unsigned(25 downto 0) ) return std_logic_vector;
  procedure write(      addr : unsigned(25 downto 0); 
                        data : std_logic_vector(31 downto 0)
                 );
  
end protected ddr_model_t;
 
 
 
type ddr_model_t is protected body
    
  type bank_t;
  type row_t;
  
  type row_ptr_t is access row_t;
  type bank_ptr_t is access bank_t;
  
  type row_t  is array(0 to 1023) of std_logic_vector(31 downto 0);
  type bank_t is array(0 to 8191) of row_ptr_t;
  
  ---------------------------------------------------------------------
  --Total mem is 8 banks x 8192 rows x 1024 columns x 32 bits/word
  --
  -- = 256 Mbyte
  ---------------------------------------------------------------------
  type mem_t is array(0 to 7) of bank_ptr_t;
  
  variable mem              : mem_t;
  
  impure function read(addr : unsigned(25 downto 0) )  return std_logic_vector is
    variable bank           : integer;
    variable row            : integer;
    variable column         : integer;
    
    variable ret            : std_logic_vector(31 downto 0);
  begin
    
    bank     := to_integer( addr(25 downto 23) );
    row      := to_integer( addr(22 downto 10) );
    column   := to_integer( addr( 9 downto  0) );
    
    ---------------------------------------------------------
    --Bank has not been written to, therefore not created
    ---------------------------------------------------------
    if mem(bank) = null then
      ret := (others => 'X');
      
    ---------------------------------------------------------
    --Row has not been written to, therefore not created
    ---------------------------------------------------------
    elsif mem(bank)(row) = null then
      ret := (others => 'X');
      
    ------------------------------------------
    --Return what has been written already
    ------------------------------------------
    else 
      ret :=  mem(bank)(row)(column);
    end if;
      
    return ret;   
  end function read;
 
 
  procedure write(      addr : unsigned(25 downto 0); 
                        data : std_logic_vector(31 downto 0)
                 ) is
    variable bank           : integer;
    variable row            : integer;
    variable column         : integer;
  begin
    
    bank     := to_integer( addr(25 downto 23) );
    row      := to_integer( addr(22 downto 10) );
    column   := to_integer( addr( 9 downto  0) );
    
    --------------------------------------------------
    --Create the bank if it doesnt already exist
    --------------------------------------------------
    if mem(bank)   = null then
      mem(bank)   := new bank_t;
    end if;
    
    ---------------------------------------------
    --Create the row if it doesnt already exist
    ---------------------------------------------
    if mem(bank)(row) = null then
      mem(bank)(row)     := new row_t;
    
      mem(bank)(row).all := (row_t'range => (others => 'X'));
    end if;
    
    mem(bank)(row)(column) := data;
  end procedure write;
  
end protected body ddr_model_t;