kevin54
Member level 2
How to create a footprint with thermal pad & tented thermal vias in Altium Designer
Problem: Device with a large thermal pad (which is not covered with soldermask), needs small thermal vias in the pad to sink heat away, and those vias should be covered with a dot of soldermask to prevent solder wicking.
The obvious approach (place a via in the thermal pad and check the box for "Force complete tenting on top") doesn't work. It might look OK in Altium but there is no tenting in the Gerber files.
I haven't see this problem reported anywhere, and it was a pain to figure out a workaround so I thought I would post it here.
Solution:
1) When creating the footprint, the Thermal Pad should have a round hole defined (typical thermal via hole size is 0.3mm or smaller) so that Altium knows the top and bottom side pads are supposed to be connected. Size and shape of the Top and Bottom of the Pad will normally be rectangular, of the appropriate size for the device. Place additional vias on the pad as required to create a thermal via array.
2) The check box for "Force complete tenting on top" REALLY MEANS "don't automatically generate any solder mask opening". Check this box for BOTH the thermal pad and all thermal vias, we will manually create our own soldermask openings.
3) On the Top Solder Mask layer, place a criss-cross of (rectangular) Fills over most of the thermal pad, keeping clear of the area close to the holes where we want soldermask. If you want a "Solder Mask Defined" pad (soldermask covers the edge of the pad, recommended for the thermal pad by some vendors), make this area slightly smaller than the copper pad.
4) We now have a thermal pad which is mostly free of soldermask, with square patches of soldermask over the vias. Make these round by Placing Full Circle arc "doughnuts" over each via. Typically this will be 0.1mm larger in diameter than the hole. For a 0.3mm diameter hole, you could use radius of 0.3mm and a width of 0.2mm which results in a 0.4mm diameter dot of soldermask.
5) If you want the bottom side of the thermal pad covered with soldermask, check the box "Force complete tenting on bottom" for both the Thermal Pad and the vias. If you want the bottom side of the thermal pad free of soldermask, Uncheck the box "Force complete tenting on bottom" for the Thermal Pad.
6) On the Paste Mask Top layer, you don't want 100% coverage for a large pad, so for the thermal pad, delete the rectangular paste mask opening. In its place, put an array of small squares of Fill, and don't put them over the holes (which are soldermasked, so there's no point). You want around 75% of the pad area covered by solder paste.
7) If the thermal vias might be connected to power or ground planes, edit or create a PCB "Plane" Rule to set the thermal vias' Connect Style to "Direct Connect" for maximum thermal conductivity - you don't want a "Relief Connect".
This approach will generate correct Gerber files (even though it might not look right in Altium).
FYI here's a Cirrus Logic app note ("Thermal Considerations for QFN Packaged Integrated Circuits")
http://www.cirrus.com/en/pubs/appNote/AN315REV1.pdf
Here's an Actel app note ("Assembly and PCB Layout Guidelines for QFN Packages")
http://www.actel.com/documents/QFN_AN.pdf
A Texas Instruments app note ("PowerPAD Thermally Enhanced Package"):
**broken link removed**
And an Amkor app note: ("Application Notes for Surface Mount Assembly of Amkor's MicroLeadFrame (MLF) Packages")
http://www.amkor.com/index.cfm?objectid=42EDA4C7-5056-AA0A-E2A372F025BF8729
Problem: Device with a large thermal pad (which is not covered with soldermask), needs small thermal vias in the pad to sink heat away, and those vias should be covered with a dot of soldermask to prevent solder wicking.
The obvious approach (place a via in the thermal pad and check the box for "Force complete tenting on top") doesn't work. It might look OK in Altium but there is no tenting in the Gerber files.
I haven't see this problem reported anywhere, and it was a pain to figure out a workaround so I thought I would post it here.
Solution:
1) When creating the footprint, the Thermal Pad should have a round hole defined (typical thermal via hole size is 0.3mm or smaller) so that Altium knows the top and bottom side pads are supposed to be connected. Size and shape of the Top and Bottom of the Pad will normally be rectangular, of the appropriate size for the device. Place additional vias on the pad as required to create a thermal via array.
2) The check box for "Force complete tenting on top" REALLY MEANS "don't automatically generate any solder mask opening". Check this box for BOTH the thermal pad and all thermal vias, we will manually create our own soldermask openings.
3) On the Top Solder Mask layer, place a criss-cross of (rectangular) Fills over most of the thermal pad, keeping clear of the area close to the holes where we want soldermask. If you want a "Solder Mask Defined" pad (soldermask covers the edge of the pad, recommended for the thermal pad by some vendors), make this area slightly smaller than the copper pad.
4) We now have a thermal pad which is mostly free of soldermask, with square patches of soldermask over the vias. Make these round by Placing Full Circle arc "doughnuts" over each via. Typically this will be 0.1mm larger in diameter than the hole. For a 0.3mm diameter hole, you could use radius of 0.3mm and a width of 0.2mm which results in a 0.4mm diameter dot of soldermask.
5) If you want the bottom side of the thermal pad covered with soldermask, check the box "Force complete tenting on bottom" for both the Thermal Pad and the vias. If you want the bottom side of the thermal pad free of soldermask, Uncheck the box "Force complete tenting on bottom" for the Thermal Pad.
6) On the Paste Mask Top layer, you don't want 100% coverage for a large pad, so for the thermal pad, delete the rectangular paste mask opening. In its place, put an array of small squares of Fill, and don't put them over the holes (which are soldermasked, so there's no point). You want around 75% of the pad area covered by solder paste.
7) If the thermal vias might be connected to power or ground planes, edit or create a PCB "Plane" Rule to set the thermal vias' Connect Style to "Direct Connect" for maximum thermal conductivity - you don't want a "Relief Connect".
This approach will generate correct Gerber files (even though it might not look right in Altium).
FYI here's a Cirrus Logic app note ("Thermal Considerations for QFN Packaged Integrated Circuits")
http://www.cirrus.com/en/pubs/appNote/AN315REV1.pdf
Here's an Actel app note ("Assembly and PCB Layout Guidelines for QFN Packages")
http://www.actel.com/documents/QFN_AN.pdf
A Texas Instruments app note ("PowerPAD Thermally Enhanced Package"):
**broken link removed**
And an Amkor app note: ("Application Notes for Surface Mount Assembly of Amkor's MicroLeadFrame (MLF) Packages")
http://www.amkor.com/index.cfm?objectid=42EDA4C7-5056-AA0A-E2A372F025BF8729
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