HOW TO CORRECT THIS ERROR

[simu]

hi,
i have written codes for a modular division algorithm and am getting the following error. Since am a beginner in verilog, am unable to correct my error. Also i have to correct the code as soon as possible.
can any one help me?

Error
Loop has iterated 64 times. Use "set -loop_iteration_limit XX" to iterate more.

Also i have attached my algorithm and its code with this...

 

[FvM]

Hello,

from error report I see, that this is basically the same problem that we discussed a week ago: Using an iterative loop without an unconditional termination. For this reason, the code can't be either simulated or synthesized.

Before looking into the code, may I first repeat my recent question: Can we have a brief description of the algorithm or a literature reference?

Regards,
Frank

P.S.: Can you abandon one of the redundant threads?

 

[echo47]

Wow, all that code in an 'initial' statement?

Try putting $display() statements into the 'while' loop so you can watch what's happening and identify bugs. Something like this:
$display(" r=", r, " a=", a, " b=", b, " s=", s, " l=", l, " p=", p);

I see various language translation problems such as:
"if (l >= 0)" will always be true because 'l' is unsigned.
"p = -p" will probably do bad things because p is unsigned.

 

[FvM]

The signed arithmetics problem was already mentioned, basically Verilog assumes unsigned type for reg and nets unless keyword signed is explicitely given. Furthermore I can't see the equivalence of shown algorithm and Verilog code.
E.g.: boolean expresion a ≡ 0 (mod 2) is different from (a << 2 == 0 << 2).

I also can't see easily, that the iteration used in the algorithm is finite, although I assume this is the case, cause the problem is known to be solvable. A different question is, if it's also suitable for a full parallel implementation, but could be possible at least for a small wordlength.

Similar implementations of modular division, I found described in literature (I didn't see HDL code yet, otherwise I would show it here) are generally operating serial.
as an example: **broken link removed**

Regards,
Frank