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Each extractor,LVS tool has got the utility which is able to convert Verilog to Spice
(Assura, Hercules, Calibre), also HSIM has got utility called v2s.
Do you need it for the digital design with Scells and known macro blocks ?
It is possible to write a script to extract the headers and connectivity, but ignore the content of the leaf cells.
Currently I am working free licence tool available on the web called Dolphin Smash.This tool supports Verilog Spice,SystemC,VHDL-AMS,VHDL and verilog simulation....
There are some easy tutorials given with the tool..
I hope u can try that...u can find the link in the earlier post of mine.
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