how to Convert synthesized VHDL/Verilog to spice netlist

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verilog to spice

Dear All,

I'm trying to get Spice netlist file from Verilog/VHDL. After I
synthesized the vhdl file using DesignCompiler, what tools available that
can help me to get the spice netlist. I need the interconnect
information incorporated in the spice netlist. Any help will be very
useful
Thanks in advance,
 

nettran

I am not sure, I think u can get the spice netlist after P&R
 

vhdl spice netlist

My colleague wrote programs in C language to convert Verilog codes into SPICE netlist. I'd like to know if there is any public tools available yet.
 
spice netlist format

hsim have this tools : v2h ....
Or use ECS from Cohesion ..

BRs
 

vhdl netlist to spice netlist

Hi,

you can import the synthesized verilog into Cadence and then export it as spice netlist in "analog" format.
 
vhdl to netlist

v2lvs in calibre
 

v2lvs -a

yes, use v2lvs in Calibre.
v2lvs -l umc.spi -v verilog1.v -v verilog2.v -s hardblock.spi top_cts.v -o top_cts.spi
 

pspice vhdl tools

jackson_peng said:
use "nettran" command, provided by hercules.
Click to expand...

thx very much .

thx every body .

I use nettran in hercules .

nettran -verilog file.v -verilog-b0 vss -verilog-b1 vdd -outType spice -outName file.spi

is it the right commond ?

I've got the spice netlist . but still there is some warnings .

thx all .

when i simulate in nanosim , is it necessary to add spice model ?
 

vhdl to spice netlist converter

v2lvs in calibre
verilogIn in cadence
and similar tool in Herculs of synopsys but I cannot remember the name
 

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