how to convert std_logic_vector to integer

[shastri.vs]

HI,
I am designing a ckt for GF elements.
i want to do mod operation on the inputs taken from std_logic_vector ports. But the synthesizer is not allowing me to do it as mod or multiply operations on std_logic_vectors are not possible.

So I want to convert this to integer, How to do it ?? can anybody help

 

[palai_santosh]

You can try this
use IEEE.std_logic_signed.all;
CONV_INTEGER();

 

[FvM]

Integer is an abstract type, that can't be used in sythesized logic without specifying a range. In any case, the underlying bit_vector is hidden, so you can't access the individual bits. A range constrainted integer is an elegant method to implement e.g. a counter. But the basic type to be used for arithmetics is signed or unsigned. Also when converting std_logic_vector to integer, you have to convert to signed or unsigned before to clarify the sign (unless you're using one of the "lazy engineer's" signed/unsigned libraries).

 

[Maxwell077]

Actually you have to use like

name_of_std_logic_vector <= conv_integer(Name_of_integer, NumberOfBits)

 

[FvM]

Actually you have to use like

No VHDL standard library has a similar function with a size argument.
ieee.numeric_standard has

  function TO_INTEGER (ARG: UNSIGNED) return NATURAL;
  function TO_INTEGER (ARG: SIGNED) return NATURAL;

ieee.std_logic_arith has

  function CONV_INTEGER(ARG: UNSIGNED) return INTEGER;
  function CONV_INTEGER(ARG: SIGNED) return INTEGER;

As said before, the integer type has no bit length.

 

[xtcx]

A range constrainted integer is an elegant method to implement e.g. a counter. But the basic type to be used for arithmetics is signed or unsigned. Also when converting std_logic_vector to integer, you have to convert to signed or unsigned before to clarify the sign (unless you're using one of the "lazy engineer's" signed/unsigned libraries).

Do you say using VHDL libraries for converting data types is not that efficient or what?. I can't understand your point of not using the VHDL libraries FVM. You can do like this,

.
entity test is
port ( A : in std_logic_vector(7 downto 0))
end entity
.
.
Signal B : integer range 0 to 255;
begin
B = CONV_INTEGER(A);
end bhavioral.

Here using a limit in signal declaration, you can limit/round up the INTEGER assignment to any figure. Here the B reg takes only 8-bit in hardware. I wouldn't think

A range constrainted integer is an elegant method to implement e.g. a counter.

could be useful here. Thank you

 

[FvM]

Do you say using VHDL libraries for converting data types is not that efficient or what?.

It's not a matter of efficiency in terms of resource usage. The VHDL compiler can be expected to fully minimize any logic and arithmetic
representation, independant of used libraries. The terms elegance and laziness are a meaning effective coding style, regarding

- small text
- readability
- easy implementation of mixed signed/unsigned arithmetic

 

[xtcx]

That's ok....The way the coding be organized is actually a good way of writing. But all xilinx generated codes never look so organized or aligned. Maybe because it's generated not written....!