comp_engineer
Newbie level 5
- Joined
- Mar 23, 2013
- Messages
- 10
- Helped
- 0
- Reputation
- 0
- Reaction score
- 0
- Trophy points
- 1,281
- Activity points
- 1,385
Hi everyone
I'm working on converting a Single Cycle MIPS Processor I wrote in Verilog HDL into a Pipelined MIPS Processor.
I'd just like some detailed guidance, programmatically speaking, about how I should go about this.
I understand the main difference between the Single Cycle and the Pipelined Processors is the addition of the "Stage Registers" for the 5 stages of the Pipeline (Fetch, Decode, Execute, Memory, Writeback), otherwise the rest of the Processor is very similar, it even has the same control unit. Please don't use advanced lingo, I'm only a student and the use of such words would only confuse me further.
I've included design schematics of my Single Cycle and Pipelined Processors as attachments.
Here is the way I have currently done so, please tell me if this way is correct or wrong or what other method do you believe is better or more straightforward:
This is the Register Module, I am instantiating for the Stage Registers
This is my top level where I call all the module and essentially layout my processor
This code is modeled exactly as how the design schematic is layed out so Please tell me what am I doing right or wrong?
I know this is kind of a vague question, so please ask me if I need to clearify anything or add more information.
Any help or assistance would be much appreciated.
I'm working on converting a Single Cycle MIPS Processor I wrote in Verilog HDL into a Pipelined MIPS Processor.
I'd just like some detailed guidance, programmatically speaking, about how I should go about this.
I understand the main difference between the Single Cycle and the Pipelined Processors is the addition of the "Stage Registers" for the 5 stages of the Pipeline (Fetch, Decode, Execute, Memory, Writeback), otherwise the rest of the Processor is very similar, it even has the same control unit. Please don't use advanced lingo, I'm only a student and the use of such words would only confuse me further.
I've included design schematics of my Single Cycle and Pipelined Processors as attachments.
Here is the way I have currently done so, please tell me if this way is correct or wrong or what other method do you believe is better or more straightforward:
This is the Register Module, I am instantiating for the Stage Registers
Code:
module Register#(parameter DATA_IN=32, DATA_OUT=32)
(clk, reset, in1, in2, out1, out2);
input clk, reset;
input [DATA_IN-1:0] in1;
input [DATA_IN-1:0] in2;
output reg [DATA_OUT-1:0] out1;
output reg [DATA_OUT-1:0] out2;
wire clk, reset, in1, in2; //these are wires to connect
//the register to control
always@(posedge clk or posedge reset) begin
if(reset) begin
out1 <= 32'b0;
out2 <= 32'b0;
end
else begin
out1 <= in1;
out2 <= in2;
end
end
endmoduleThis is my top level where I call all the module and essentially layout my processor
Code:
/***********************************************************************************************
Fetch Stage
Processor Reads the instruction from instruction memory
************************************************************************************************/
InstructionMemory iMem(PC, Instr);
ProgramCounter ProgCounter(clk, reset, PCnext, PC);
PCPlus4 PCP4(PC, PCPlus4);
//pipelined register
Register regIFID(clk, reset, Instr, PCPlus4, InstrD, PCPlus4D);
assign PCBranch = PCSrc ? (SignImm + PCPlus4) : PCPlus4;
//assign PCnext = Jump ? ({6'b0, Instr[25:0]} + PCPlus4) : PCBranch;
assign PCnext = Jump ? ({SE, Instr[25:0]} + PCPlus4) : PCBranch;This code is modeled exactly as how the design schematic is layed out so Please tell me what am I doing right or wrong?
I know this is kind of a vague question, so please ask me if I need to clearify anything or add more information.
Any help or assistance would be much appreciated.