How to Convert from "STD_LOGIC_VECTOR to STD_LOGIC&quot

[xtcx]

std_logic_vector to std_logic

Guys! Could anybody help me how to convert a register configured as STD_LOGIC_VECTOR(0 DOWNTO 0) to STD_LOGIC?...In FIFO IP generation, I configured 1 bit width and 32 bit depth...The design has created Din and Dout as type "STD_LOGIC_VECTOR(0 DOWNTO 0)" but in my design all types are of STD_LOGIC;...Both are 1-bit, but don't know how to change. If I change the type in IP generated FIFO file as "STD_LOGIC" as in my design, it show errors in translation!...Please help friends!...Tanks

 

[elec4fun]

convert std_logic to std_logic_vector

Hi,

If you want to translate a n bits STD_LOGIC_VECTOR signal to n STD_LOGIC signals you can do something like this for example:

signal test_vector: std_logic_vector(3 downto 0);
signal b0,b1,b2,b3 : std_logic;
....
b0 <= test_vector(0);
b1 <= test_vector(1);
b2 <= test_vector(2);
b3 <= test_vector(3);

Regards,
Franck.

 

[xtcx]

std_logic to std_logic_vector

Thanks Franc, but i know that...however the case is "STD_LOGIC_VECTOR(0 DOWNTO 0)". How can you pass a signal of this type to "STD_LOGIC"?....Do you have any idea?....

 

[kvingle]

std_logic_vector(0 downto 0)

STD_LOGIC_VECTOR (0 downto 0 ) has a single bit
so as suggested in previous post you should be able to convert it in std_logic as

ur_std_logic <= ur_std_vector(0);

 

[xtcx]

convert std_logic_vector to std_logic

Hey try for it yourself ya...You will find errors.
Like I said,just see how I coded. Only Din,Dout corresponds to std_logic_vector(0 downto 0).These are generated from FIFO IP core.any values passed to Din or Dout must also be of same data type,otherwise it shows errors....
------------------------------------
entity SDR
PORT (
sclk : in std-logic;--codec clk
sdi : out std_logic; --data to codec
sdo : in std_logic; -- data from codec
din : in std-logic_vector(0 downto 0); ---FIFO data input
dout : out std_logic_vector(0 downto 0); --FIFO data output
wr_clk,rd_clk : out std_logic; -- Indpendant clk mode for FIFO stacking
wr_en,rd_en : out std_logic;-- enable pins
full,empty : std_logic --flags
);
architecture SDR of Behavioral is
signal count1,count2 : integer range 0 to 40 :=0;
begin

process(sclk) is
begin

if rising_edge(sclk) then
count1 <= count1+1;
case count1 is
when 0 => rd_en <= '1'; -- enable read data from fifo
when 1 => sdi <= din; -- start reading data and send it to sdi bus(codec)
when 3 => sdi <= din;
when 33 => count2 <= 0;
rd_en <= '0';
when 34 =>
count2 <= count2+1;
count1 <= 34;
case count2 is
when 0 => wr_en <= '1';
when 1 => dout <= sdo;
when 2 => dout <= sdo;
when 33 => count 1 <= 0;
wr_en <= '0';
when others => null;
end case;
when others => null;
end case;
end if;
end process;
----------------------------------
Here sdi is assigned to dout....But both are of std_logic and std_logi_vector(0 downto 0) type.If you pass values then it shows errors ..no use!....Got any idea?.

 

[Zerox100]

vhdl convert std_logic to std_logic_vector

Feel free. You can convert "std_logic_vector (0 downto 0)" to "std_logic". It will work fine. But you should convert all vector. if you had a problem let me know...

 

[xtcx]

vhdl std_logic to std_logic_vector

Feel free. You can convert "std_logic_vector (0 downto 0)" to "std_logic". It will work fine. But you should convert all vector. if you had a problem let me know...

Hello buddy, just try for yourself, a sample program in vhdl in which declare a data type of "SDATA : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)"

Now inside your process,just try passing a single bit value and you will see getting errors in syntax.....Please try it yourself, and let me know if there is any solution....Thanks

 

[elec4fun]

translate std_logic_vector to std_logic

And what about: dout(0) <= sdo ?

 

[robinh]

what is std logic vector

Use a signal for the input and for the output. You do not need any function to do this.

A simple assignment should be sufficient for both of them.

 

[amir81]

convert to std_logic_vector

this code will work:

process(sclk) is
begin

if rising_edge(sclk) then
count1 <= count1+1;
case count1 is
when 0 => rd_en <= '1'; -- enable read data from fifo
when 1 => sdi <= din(0); -- start reading data and send it to sdi bus(codec)
when 3 => sdi <= din(0);
when 33 => count2 <= 0; rd_en <= '0';
when 34 => count2 <= count2+1; count1 <= 34;
case count2 is
when 0 => wr_en <= '1';
when 1 => dout(0) <= sdo;
when 2 => dout(0) <= sdo;
when 33 => count1 <= 0; wr_en <= '0';
when others => null;
end case;
when others => null;
end case;
end if;

end process;

 

[Zerox100]

convert std_logic to unsigned

if you define din like a vector even if it was single bit vector you cant assign it to a bit. but in any vector you can choose bit and assign it to another bits like below:

--///////////////////////////

when 1 => sdi <= din(0);

--///////////////////////////

 

[xtcx]

std_logic to std_logic_vector(0 downto 0)

And what about: dout(0) <= sdo ?

I donnu,but let me see if it works....If it does,you two get the help points

Added after 5 minutes:

if you define din like a vector even if it was single bit vector you cant assign it to a bit. but in any vector you can choose bit and assign it to another bits like below:

--///////////////////////////

when 1 => sdi <= din(0);

--///////////////////////////

Oh thanks ZEROX100, I thought like Din is already a single bit defined in std_logic_vector(0 downto 0). So it's suffice to access it by any registers of std_logic type which is also a bit logic, well using Din(0) seems to clear the issue...

Added after 11 minutes:

Hey Thanks you all guys, I've got the problem cleared....Need to define as din(0)....You all receive the help points....Thanks