I have designed my code in system verilog (Modelsim) and instantiated 2 dimensional array vector, there it shows no problem in compilation and simulation but for synthesizing (Xilinx) the code it shows error(illegal reference to net array) for 2 d array vector...
so I would like to convert this to 1 d array vector...kindly provide me the same.
Please someone help me its urgent.
Thank you.