How to contrain minimum pulse width for output data in synthesis ?

Hello~!

I'd like to know:
How do we set timing constraint for output data minimum width during Design Compiler synthesis ?
I've attached a picture below to illustrate my question.



In the above picture, the design is supposed to output data within 1T~2T. ( due to clock skew inside, pad delay ... )
Here we define the delay from pin Q of last FF to output as T1. The output data should remain stable at least T2 (e.g. 0.6T) long.
Since end of T2 is related to T1, how do we constrain this timing T2 ?



Currently, the only way I thought is to define the T1 as fixed value, such as 1.5T
=> set_output_delay -0.5T -max -clock Clock [get_ports Output] ? or set_max_delay 1.5T [get_ports Output] ?
And then we can define T2 as 2.1T
=> set_output_delay -1.1T -min -clock Clock [get_ports Output] ? or set_min_delay 1.1T [get_ports Output] ?

But we have to make T1 and T2 fixed before applying this method and it's also not flexible.
Would you have another method for this topic ?

Thanks for your help.
Best Regards.
PoLo

Just put the thread to the topic again.
Waiting for your help.