How to constraint interface with create_generated_clock

I have a design as following,
and I want to use create_generated_clock to constraint the interface (din, dout) in design compiler

=====================================================
module (clki, rst, din, dout, clko);
input clki, rst, din;
output dout, clko;

....
always @(posedge clki or posedge rst)
begin
if (rst)
clko <=1'b0;
else
clko <= ~clko;
end
endmodule
=====================================================

din, dout are the interface related with clko.
I tried to declare clko as a generated clock to constraint din & dout

=====================================================
create_clock clki -period P
set_ideal_network clki
set_dont_touch_network clki
create_generated_clock clko -source clki -divide_by 2
set_input_delay X [get_ports din] -clock clko -add
set_output_delay Y [get_ports dout] -clock clko -add
=====================================================

After compile, I check the timing report.
But here is no clock latency between clki & clko (I expect here is at least CK->Q delay),
My questions are:
1. How to let design compiler optimize with the CK->Q latency?
2. If I set_propagate_clock [get_clocks clki], the timing report will show CK->Q latency, but here are many max_transition/max_fanout violations on other points
3. How could I constraint interface by create_generated clock with clock latency from source to generated clock?

To my understanding:
1): you need set "set_propagate_clock [get_clocks clki]"
2): you need specify clko as ideal network, as you are doing RTL synthesis, no clock tree now. Maybe something like: set_ideal_network [get_pins clko_reg/Q].

Thanks for your reply.
But if I set_propagate_clock [get_clocks clki],
there are so many design rule violation at other internal FFs, such as max_transition, max_fanout, max_capcitance, which caused by clki is an ideal network.
How could I solve this?

asic_service said:

To my understanding:
1): you need set "set_propagate_clock [get_clocks clki]"
2): you need specify clko as ideal network, as you are doing RTL synthesis, no clock tree now. Maybe something like: set_ideal_network [get_pins clko_reg/Q].

Click to expand...

taenet said:

Thanks for your reply.
But if I set_propagate_clock [get_clocks clki],
there are so many design rule violation at other internal FFs, such as max_transition, max_fanout, max_capcitance, which caused by clki is an ideal network.
How could I solve this?

Click to expand...

Hi, you need pay attention to point 2). set_ideal_network on the generated clock: clko.