dsula007
Newbie
I have the following circuit situation:
pin (input) ---gate0 --- |--- gate1 ----- regular net here
|--- gate2 ----- clock net here.
A pin is used as both a clock and as a regular data signal. The pin drives into gate0 which then drives into gate1 and gate2.
After gate1 the net should be considered a clock net as it's going to CK input of many FF.
After gate2 the net is a data net and it's going to D input of FF (clocked by some other clock).
I was hoping to be able to create a clock on the pin using the SDC command create_clock which then propagates the clock attribute through the whole circuit.
I was then also hoping to remove the clock attribute from the net starting at gate2 to revert it to a regular data net. Unfortunately there's doesn't seem to be a command to do that.
Alternatively I can create the clock (using create_clock) starting at the output of gate2. That works, but leaves out the pin and the gate0 from the clock tree synthesis process.
I was wondering if anybody knew how to deal with this situation and how to correctly constraint this circuit.
Thank you very much.
pin (input) ---gate0 --- |--- gate1 ----- regular net here
|--- gate2 ----- clock net here.
A pin is used as both a clock and as a regular data signal. The pin drives into gate0 which then drives into gate1 and gate2.
After gate1 the net should be considered a clock net as it's going to CK input of many FF.
After gate2 the net is a data net and it's going to D input of FF (clocked by some other clock).
I was hoping to be able to create a clock on the pin using the SDC command create_clock which then propagates the clock attribute through the whole circuit.
I was then also hoping to remove the clock attribute from the net starting at gate2 to revert it to a regular data net. Unfortunately there's doesn't seem to be a command to do that.
Alternatively I can create the clock (using create_clock) starting at the output of gate2. That works, but leaves out the pin and the gate0 from the clock tree synthesis process.
I was wondering if anybody knew how to deal with this situation and how to correctly constraint this circuit.
Thank you very much.
