How to constrain a control signal ?

[mic_huhu]

How to constraint

Hi,all

when reports says a control signal must cost more than one cycle to register,but it is one clock period in fact. How to constraint this ? It is not muticycle.

with many thanks

JOhnny

 

[kib]

Re: How to constraint

if u r targeting xilinx fpga u can use FROM-TO timing constraint

 

[gknerd]

Re: How to constraint

If the control signal is a static signal, you can just set it as False Path to disable timing check on this path.

 

[omid219]

How to constraint

It means that the combinational path take more than one clock period time to settle. So you have to reduce the frequency or break the critical path or force your synthesis tool to optimize that path to fit your timing requirement.