How to constain a internal generated clock in DC script?

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I have a module. The clk of TOP is connected to the internal module CLK_GEN. The output clk_div of CLK_GEN is divided by 0, 4, 8.

The clk_div is used as other internal modules input clock and the output port of the TOP module.

I hope to know how to constain this signal in the top-down DC script?

Thanks in advance.
 

Code: 
create_clock DIV2_CLK -period   DIV2_PERIOD \
                                   -waveform { 0  DIV2_HCYCLE } 
set_dont_touch_network DIV2_CLK

If you need more inf., PM me!
Hope this help
 

use " create_generated_clock " to constrain the derived clocks.
 

Read the book by himanshu bhatnagar on ASIC synthesis and STA...the book is available somewhere on this forum...
 

please use set_propagated_clock to obtain generate clock source latency
 

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