I am designing a N-bit ADC and want to test it. In Allan's book, it states that I can put a (N+2)-bit ideal DAC after my ADC and then check the difference between the input and output. Can anybody tell me how to connect the N-bit ADC to an (N+2)-bit DAC? I mean where should I connect that two extra-bit?
The reason for N+2 is that it is linear to the N+2 bits and therefore to 1/4 bit at the N bit level. I have used the trick of designing in a N+1 bit ADC to a system and discarding the LSB. This made the data more linear than with an N bit DAC.
You can also capture the digital data from the ADC and do a FFT on it with N+2 bit or more arithmetic.
a better approach to test adc avoiding intergrating dac in the chip is to analysing the data from logic analyser directly. u can search a free program based on MATLAB in website,such as www.maxim.com.
braudelk is right, you can never get a precise result by puting DAC after ADC. For ADC, we care SNDR, SFDR, INL, DNL ... . Visit Maxim, you will get a solution.
what is kyrandia said is right. static parameter INL and DNL,and dynamic parameter ENOB are important. at the same time other parameters such as SNDR and SFDR and so on are attented by us.