The problem is that the occupation level on the board grows adding every new DSP block(FIR filters,shift registers,multipliers,...) ,and so the FPGA board we use doesn't contain it.
I don't know how connect a block on the first FPGA (such as a filter or an adder) to an other block realized on the second(such as a FIR filter).
I hope to receive an answer.
Thanks.
You can use Synplicity Certify synthesis tool and it automatically partition/repartition your RTL/logic across two FPGAs based on the available resources.
Cheers,
-DT