How to confirm the w/l of this MOS Transistor

[wjx197733]

Hi all, I am a fresh man to design analog circuit.

These days I design a simple OP, as you can see in the attachment. The main parameter of the OP is:
VDD=5V, SR>=10V/µs (CL=5pF), f-3dB>=100kHz (CL=5pF), a small signal gain of 100V/V, 1V<=ICMR<=4.5V, and Pdiss<=1mW. Use the parameters of KN’=110µA/V2, KP’=50µA/V2, VTN=0.7V, VTP=-0.7V,
λN=0.04V-1 and λP=0.05V-1.

The w/l of most MOS has been confirmed, but confirm the w/l of M8 is so difficult for me. if I replace M8 by a current socrce, there have no problem, so I think the w/l of most MOS is rignt.

How to design the w/l of M8? help me please!!!

 

[cretu]

I couldn't see any M8 in your schematic...can you check it?

 

[shaq]

Which one is M8?
I cannot find that!

 

[starcoming]

Do you really mean M3?

 

[wjxcom]

I think it is not M8, but M7, because I have the same question.

 

[Humungus]

M3 and M4 play a role on:
1) frequency response: they introduce a doublet. given you GBW, i thing the doublet introduced by M3/4 appears after ft. You can deduce maximum W*L
2) PSRR: you don't have any specification
3) gain: DC gain is gm1/(gd1+gd4). This gives you minimum L
4) Noise: this gives you minimum W*L
5) Offset: this gives you minimum W*L as well as minimum L

Continue to make the analysis with the remaining parameters you have.

This procedure will give you as a resuslt a space of acceptable solutions.

 

[sutapanaki]

Well, if it is M7, then it is not working as a current source. In fact as it is now, each one of M6 and M7 works with Vgs=2.5v and M5 too. But you want your lower limit of the ICMR to be 1V and if so then M5 is already in linear (ohmic) mode which is not good. If you insist on this way of bising you have to change the size of M7. You know the current and the size of M6 - calculate the Vgs6. Then Vgs7=Vdd-Vgs6 and Vsb7 is equal to Vgs6 - use it to calculate the Vt of M7. Then with the current, Vgs7 and Vt7 calculate W/L.