How to compile encrypted verilog file in Modelsim?

rezwanh · Jul 11, 2013

I am using a 3rd party DDR3 SDRAM IP and all I got is a verilog protected .vp file and verilog header file .vh. I found following command in modelsim manual to protect a verilog file(you need to use `protected and `endprotected pragma in your verilog code) but I don't know how to compile a protected file.

vlog +protect xxxx.vp

I am wondering if anyone knows how to compile this .vp file.

yura717 · Jul 11, 2013

rezwanh said:
vlog +protect xxxx.vp

This command Will create protected file .... its not used to compile your design.

aruipksni · Jul 11, 2013

yura717 said:
This command Will create protected file .... its not used to compile your design.

vlog *.vp

???

yura717 · Jul 12, 2013

You can compile encrypt.vp just like any other verilog file

How to compile encrypted verilog file in Modelsim?

rezwanh

Newbie level 3

yura717

Advanced Member level 2

aruipksni

Full Member level 6

yura717

Advanced Member level 2

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How to compile encrypted verilog file in Modelsim?

rezwanh

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yura717

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aruipksni

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yura717

Advanced Member level 2

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