Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

How to compensate the parasitic input impedance?

Status
Not open for further replies.
E

EDA_hg81

Advanced Member level 2
Advanced Member level 2
Joined
Nov 25, 2005
Messages
507
Helped
2
Reputation
4
Reaction score
2
Trophy points
1,298
Activity points
4,808
The parasitic impedance of input driving clock could be several nanofarads.

How can I compensate this several nanofarads and make input driving clock sharp?

The input voltage could be 12V.

Thanks.
 

You cannot really "cancel" the input capacitance, you just need a stronger buffer that can actually drive that load.
 

    E

    EDA_hg81

    Points: 2
    Helpful Answer Positive Rating
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top