How to compare hardware complexity of two digital systems?

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msp4u4ever

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Hello all,
I have a system implemented in two different ways (using verilog).
How can I compare the hardware complexity of both the designs?
Is it possible to compare the hardware complexity by synthesizing both the designs using a single cell (2-input NAND gate etc)?This way we will know the total gate count of both the designs?
How can we do that in Synopsys Design Compiler?
If this is not the way, how do we compare the hardware complexity?
 

You could synthesize both code and calculate the gate count equivalent, area divided by nand2 area.
 
@rca thank you for the reply..
But how about the effects of other gates?
I mean, if the synthesis is done only using the nand2 gates, that would be a good measure.
But synthesis is done using other gates as well (nand2's, or3's etc).
I am a newbie, please correct me if I am wrong.
How can we tell the design compiler to use only nand2's to synthesize our design?
 
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    erikl

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I always compare the design with the gate count, because the NAND 2 input with drive 1 is the basic element, normally optimized for this technology.
I already seen some std cell liberty file without the real area information but the gate ration.
 
@rca thank you..
But my doubt ain't cleared.

- - - Updated - - -

@rca thank you..
But my doubt ain't cleared.
 

msp4u4ever said:
But how about the effects of other gates?
...
But synthesis is done using other gates as well (nand2's, or3's etc).
Click to expand...

That's ok. You get the number of all individual gates used, and you'd know there size. So add up all the gates' sizes and compare.
For a general statement on complexity, you can re-calculate a NAND2 gate count by dividing the areas by the NAND2 gate area.
 
Well, if you synthesize both codes with the same std cell libraries you could compare the two designs.
We ususally used the gate count to compare two technologies.
To have a better result, the place and route helps this when you want to reach the maximum std cell density.
 
thank you very much rca and erikl..
will try it..
 

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