giggs11
Member level 3
Hi,
I am trying to enable commmunication between two FPGAs, both being the
Stratix 1S40 on the Nios Stratix Boards. One chip implements a
controller while the other implements a datapath. I am trying to
provide control signals to the datapath-chip from the controller-chip
and retrieve back the output from the datapath-chip back to the
controller-chip. For this, I have assigned the outputs and inputs of both designs to the pins of the Proto 1 & 2 connnectors on the board and used the LVTTL IO standard. For some reason, the communication doesn't seem to take place. Subsequently, the connection between the FPGAs is then done through IDE cables connected to the 40 pin Protos. Any settings
that I should be aware of when attempting to enable communication
through Proto connector pins..?
Thanks.
I am trying to enable commmunication between two FPGAs, both being the
Stratix 1S40 on the Nios Stratix Boards. One chip implements a
controller while the other implements a datapath. I am trying to
provide control signals to the datapath-chip from the controller-chip
and retrieve back the output from the datapath-chip back to the
controller-chip. For this, I have assigned the outputs and inputs of both designs to the pins of the Proto 1 & 2 connnectors on the board and used the LVTTL IO standard. For some reason, the communication doesn't seem to take place. Subsequently, the connection between the FPGAs is then done through IDE cables connected to the 40 pin Protos. Any settings
that I should be aware of when attempting to enable communication
through Proto connector pins..?
Thanks.