Hi all,
I would like to know the key concerns while desiding different DRC rules for a new
process technology (CMOS) such as spacing between different layers, gate length,
gate oxide thicknes etc. Please help me out with your comments or with a good book/
documentation.
these are the constaints depending upon the accuracy and precision of the instruments and the technology used in the fab. If these are not met, then the the given design cannot be faricated in the given fab, for a give technology.