Pipeline ADC questions
I am just starting working on a Pipelined ADC project, did a lot of reading and already have a prelim behavioural model up in Matlab.
There are some questions that I would appreciate some help on.
1. Regarding redundant pipe stages ie. 2.5B or 1.5B
I noticed that most papers depict just one type of pipe stages ie. for a 10-bit ADC they use up 10x 1.5B or say 6bits ADC with 3x 2.5B stages. Are there any issues combining different resolution pipe stages to achieve the desired resolution?
2. Combining a redundant pipe stage with regular last stage FLASH. For example a 2.5B with a 3 bit FLASH
For get an effective 5 bit resolution I discard the LSB of the 2.5B stage and concatenate it with the 3 bit FLASH. However, I notice that the output codes are not monotonic wrt to the input signal. Is there somthing that I am missing here.
Thanks in advance.