yuenkit
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Hi, I am coding a Variable-Length Decoder (part of my Mp3 decorder project).
The input bit-stream is - 1011 0001 0111 0011
The code table
[1] [011] [0001] [011] [1] [0011]
so the decoded output should be 016104
Since there is no casez (verilog) equivalent in VHDL, I use a nested CASE statement. However, I think doing this way is quite cumbersome. I wonder if there any better way of doing this? Thank you.
The input bit-stream is - 1011 0001 0111 0011
The code table
Code:
Code Code Length Output
==== ========= =====
1 1 0
011 3 1
0101 4 2
0100 4 3
0011 4 4
0010 4 5
0001 4 6
0000 4 7[1] [011] [0001] [011] [1] [0011]
so the decoded output should be 016104
Since there is no casez (verilog) equivalent in VHDL, I use a nested CASE statement. However, I think doing this way is quite cumbersome. I wonder if there any better way of doing this? Thank you.
Code:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity lut is
port(
clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR(3 downto 0);
dout : out STD_LOGIC_VECTOR(3 downto 0)
);
end lut;
--}} End of automatically maintained section
architecture lut of lut is
-- variable found: std_logic;
signal temp1: std_logic;
signal temp2: std_logic_vector(1 downto 0);
signal temp3: std_logic_vector(2 downto 0);
signal temp4: std_logic_vector(3 downto 0);
begin
temp1 <= din(3);
temp2 <= din(3 downto 2);
temp3 <= din(3 downto 1);
temp4 <= din(3 downto 0);
process (clk)
begin
if (rising_edge(clk)) then
case temp1 is
when '1' => dout <= "0000";
when others =>
case temp3 is
when "011" => dout <= "0010";
when others =>
case temp4 is
when "0101" => dout <= "0010";
when "0100" => dout <= "0011";
when "0011" => dout <= "0100";
when "0010" => dout <= "0101";
when "0001" => dout <= "0110";
when "0000" => dout <= "0111";
when others => dout <= "1111";
end case;
end case;
end case;
end if;
end process;
end lut;