KH, in some of the mixed-signal circuits, I can design the analog circuitry in transistor level and use Analog Artist to simulate them. For some of the digital circuitry in these designs, Verilog-A seems to work fine.
But my problem really comes when you have an equally complicated digital system, where Verilog-A description/model is not sufficient (it is a subset of Verilog, anyway). Under this condition, how do you co-simulate the analog circuitry with Verilog/VHDL described digital blocks to fully verify the system performance and function in Cadence? I know Mentor Graphics provides ADMS which combines Eldo and HDL simulation capability.
I am sure Cadence can do the same. Can someone please help?