How to co-simulate VHDL/Verilog with transistor circuit?

[willyboy19]

If I have IC5.0 and LDV5.1 installed in Linux, how can I simulate a mixed-signal design which includes transistor level circuitry AND digital blocks described in Verilog/VHDL? Can this be done in Analog Design Environment? Is there a good tutorial on this? Please help!

Willy

 

[khorram]

As you know, transistor level modules are just available in Verilog language. You can do that in a hierarchical design. It means that you should write some modules or processes to describe your RT level subsection and you should write some modules (always blocks) which include transistor descriptions. If you don't need acurate timing of transistors, you can do that in VHDL/Verilog simulator without Analog part. Otherwise, you should use the analog part and i think you would have lots of problems.

Regards,
KH

 

[willyboy19]

KH, in some of the mixed-signal circuits, I can design the analog circuitry in transistor level and use Analog Artist to simulate them. For some of the digital circuitry in these designs, Verilog-A seems to work fine.

But my problem really comes when you have an equally complicated digital system, where Verilog-A description/model is not sufficient (it is a subset of Verilog, anyway). Under this condition, how do you co-simulate the analog circuitry with Verilog/VHDL described digital blocks to fully verify the system performance and function in Cadence? I know Mentor Graphics provides ADMS which combines Eldo and HDL simulation capability.

I am sure Cadence can do the same. Can someone please help?