how to clear setup and hold violations?

Status
Not open for further replies.
L

ls000rhb

Full Member level 3
Joined
Jun 17, 2005
Messages
185
Helped
7
Reputation
14
Reaction score
1
Trophy points
1,298
Activity points
2,425
how to clear setup and hold violations?
is there any simple and efficient method ?
 

ls000rhb said:
how to clear setup and hold violations?
is there any simple and efficient method ?
Click to expand...
Hi,
To clear setup violations either reduce your frequency of operation or redesign your combinational logic.
To remove hold violations delay the data path by adding buffer in the data path.

Best Regards,
 

    L

    ls000rhb

    Points: 2
    Helpful Answer Positive Rating
If you have a fixed frequency budget, the first option is usually to repartition your design, or increase compile effort. Going back to code, or even changing to a better library are after-measures.
 

set_fix_hold can help to add buffer?
 

For fixing setup violations you need to reduce the frequency of the design el;se resynthesize the design again with modified constraints. For hold violations fixes how ever, buffers, placement can help.
 

in pre-layout pls fix the setup times in synthesys. HOLD timings are fixed by back-end during post-layout phase. to fix the setup times, use incremental compilation in DC and use time budgeting and bottom-up compuilation with high compile effort. this gives the maximum possible frequency. If your design does not meet the timings, you may have to re-llok into your RTL and u can do some code level optimization to have some better timing. otherwise u have to work at reduced frequency
 

thanks very much to everyoue who gave me good suggestions!
 

You can set the lower frequency to clear setup violations.

In the P&R , you insert CTS to clear hold violations.
 

beckchm said:
You can set the lower frequency to clear setup violations.

In the P&R , you insert CTS to clear hold violations.
Click to expand...

CTS is not for fixing of hold violations. Some times because of CTS hold violations may be solved.
 

silencer3 said:
in pre-layout pls fix the setup times in synthesys. HOLD timings are fixed by back-end during post-layout phase.
Click to expand...
i agree with this. my suggests is using phycial synthsis to synthsis the design in DSM era, like PKS and PhyCompile, all of those have commands to fixed setup and hold with some knownleges of layout or placement, can short your iteration of timing closure.
 

the setup has to be checked and fixed during floorplanning, placement, CTS by changing the clock latency and the hold is considered during the CTS by inserting the buffers in the data path.
 

First you must to define your clock tree structure(clock root delay, clock skew) and then to used high driving cell to fix setup time violation and use delay cell to fix hold time violation.
 

Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…